Sung Research Group

Scope

Design, fabrication and characterization of wide bandgap power semiconductor devices

Missions

Develop efficient, rugged, and reliable power semiconductor devices;
Develop low-cost, reliable, repeatable process baseline to fabricate semiconductor devices;
Develop next generation power devices on novel materials such as SiC, homogeneous GaN, Ga2O3, AlN, and Diamond;
Explore materials, packaging of devices, and applications to demonstrate efficient semiconductor power electronics;
Explore other areas to apply and extend knowledge gained from semiconductor devices;
Educate and train undergrad, graduate students to support the missions.

Research

Recent Projects

Integrated SiC MOSFET and JBS diode – PowerAmerica BP-1
Novel edge termination for high voltage SiC devices – PowerAmerica BP-1
Foundry Process Kit for 1.2kV SiC Power MOSFETs and JBS Rectifiers – PowerAmerica BP-2
Development of 6.5kV/10kV SiC MOSFETs, JBS Diodes, and JBS Diode Integrated MOSFETs –PowerAmerica BP-3
600V SiC Lateral & Vertical JBS Diodes and MOSFETs – PowerAmerica BP-3
Manufacturing of Ultra-high-voltage SiC devices (MUSiC) – Army Research Lab / Office of Naval Research
Scalable, Manufacturable, And Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs) – ARPA-e/DOE
CPR (Cost competitive / high-Performance / highly Reliable) Power Devices on SiC and GaN – VTO/DOE
Power Nitride Doping Innovation Offers Devices Enabling SWITCHES (PNDIODES) – ARPA-e/DOE
Improving SiC Wafers and Processing for Lower Costs and Higher Reliability – AMO/DOE
Others: Projects with Companies

Research Examples

Design and Economic Considerations to Achieve the Price Parity of SiC MOSFETs with Silicon IGBTs [1, 2]

In 2015, U.S Department of Energy has launched an Institute (PowerAmerica) under the initiative of National Network of Manufacturing Institutes (NNMI) to commercialize Wide Band Gap (WBG) power devices. One of the primary goals of the Institute is to achieve significant reductions in the cost of manufacturing WBG devices and achieve price parity with Si IGBTs in the 600 – 1700 V range within 5 years of its inception and fall below today’s Si prices in 5-8 years. SiC is considered as a post-silicon device for power electronics applications because its superior material properties guarantee low power losses, higher efficiency, and smaller system volume and weight. Since the advent of the first SiC SBD in the 1990’s, numerous research groups devoted efforts to commercialize SiC devices, such as MOSFETs, JFETs, BJTs, and thyristors. However, it is believed that massive adoption of SiC power devices will not take place until there are substantial improvements in two major barriers: reliability, and price.

The most effective way of achieving price parity to Silicon counterparts is to reduce the material cost that contributes to about 50% of the overall SiC chip cost. Development of large diameter substrates to enhance yield are being pursued by wafer and chip manufacturers. On top of these efforts, device innovation not only brings chip size reduction, but also directly brings material cost reduction. However, there is a lack of quantitative analysis to suggest direction regarding improvement and consequent cost projections.

In this research, methodologies to reduce the chip size of SiC MOSFETs are discussed based on an analytical-empirical model by examining temperature coefficient, junction temperature, on-state resistance, thermal resistance of the package, and edge termination techniques (Fig. 1). In the analysis of chip size, reliability is also taken into consideration because these two factors are mutually related in some aspects. Analyses based on the developed model, lead to following conclusions; Even 5 times higher channel mobility of the planar SiC MOSFET can only save 13% of the active area because the temperature coefficient is also increased close to that of SiC bulk resistor; The development of packaging technology to lower the thermal resistance becomes an effective way of reducing the size of the chip; Edge termination and periphery area must be reduced to achieve chip-scale reduction in size. This analysis justifies the advanced packaging technologies, such as double-sided cooling, and flip-chip technique.

Finally, the cost analysis based on the proposed model clearly illustrates how the price parity to the Silicon IGBTs can be achieved. Other than the device innovation, from an exemplary cost analysis, it is found that wafer price, process yield, and wafer size also play significant roles in reducing the chip price (see Fig. 2, and Table 1). Improvement in each parameters discussed in this research should be pursued in parallel to lead to price-parity to silicon devices.

Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices [3]

In recent years, significant improvements in performance have been achieved in SiC devices, such as MOSFETs, BJTs, JFETs, IGBTs, GTOs, JBS, and PiN Diodes. In these high voltage SiC vertical devices, one of the major design concerns is the edge termination. Floating Field Rings (FFRs), or Junction Termination Extension (JTE) -based structures are commonly used edge termination approaches. However, those conventional edge termination techniques consume a significant amount of area on the chip. As a rule of thumb, the edge termination width has dimensions equal to ~5 times the drift region thickness. To reduce the chip size, and thus the cost of the SiC chip, area efficient edge termination techniques are an imperative.

Orthogonal positive bevel edge termination technique has been proposed to produce symmetric blocking structures in SiC. It has been successfully demonstrated that a chip-scale bevel edge termination becomes feasible by using a V-shaped dicing blade as shown in Fig. 3. This technique was successfully demonstrated to achieve high blocking voltage at the substrate-drift layer junction. The bevel edge termination can also be applied to support high voltage at the top PN junctions.

In this study, various innovative edge termination structures using the bevel technique, such as Bevel Junction Termination Extension (Bevel-JTE), Resistive Bevel Termination (RBT), Bevel Assisted JTE (BA-JTE), Positive Bevel Termination (PBT) were investigated. A cross-sectional view of the Bevel-JTE is shown in Fig. 4 as an example. Device simulation shows a uniform distribution of potential within the Bevel-JTE structure (Fig. 5). The aforementioned non-planar, 3D edge termination techniques significantly reduce the chip size because they require only 1X of the epi-layer in width on the SiC surface.

In general, bevel edge terminations have very low leakage current because the high hardness of SiC smooths the surface morphology when rubbed by the dicing blade (see the I-V curve in Fig. 6). Any residual damage can be then removed by RIE. It should be noted that the Bevel-JTE structure does not even require a photolithography step; CVD oxide, or other properly chosen materials, can be deposited before the dicing step. They can serve as a masking layer for the SiC surface etch treatment process and the JTE ion implantation step. After the bevel groove is inscribed on the wafer, a spray coater can substitute the spin coater for subsequent photolithography processes. Groove filling using a proper dielectric material, followed by a planarization process, can also be a good alternative. Passivation of the bevel surface, and the effect of possible inclusion of negative or positive charges should be further studied.

Since the bevel edge termination is fabricated with a dicing blade, it can be applied to any vertical device in SiC that has a drift layer of different thickness by adjusting the dicing depth. In fact, it is more attractive to use the Bevel-JTE structure for higher voltage devices because a significantly larger area of the wafer is occupied by edge termination structures using conventional approaches. Using the bevel edge termination discussed in this research, significant area can be saved, which in turn contributes to chip cost reduction.

Development of 1.2kV rated SiC MOSFETs with accumulation mode channel and inversion mode channel [4, 5]

In the past decade, there has been tremendous progress in the electrical performances of 4H-SiC power MOSFETs resulting in their commercialization. However, detailed information on the design of the channel to achieve a reasonable threshold voltage and field effect mobility is lacking in previous literature. Experimental results obtained on both accumulation mode channel design (AccuFETs) and inversion mode channel design (InvFETs) are compared in this research.

Fig. 7 shows cross-sectional diagrams of the 1.2kV SiC vertical power MOSFET and the lateral test structure used to extract the channel mobility. Doping profiles near the SiC surface were optimized by 2-D device simulations in order to accomplish reasonable threshold voltage with high channel mobility. The proposed MOSFETs were fabricated in a 6-inch wafer foundry company, XFAB, TX, U.S.A. Total 9-mask was used for fabrication of the AccuFETs and InvFETs. Fig. 8 shows on-wafer output characteristics of a typical AccuFET and InvFET. Specific on-resistances at drain current of 1A are 4.95 mΩ∙cm2, and 7.75 mΩ∙cm2, for the AccuFET, and InvFET, respectively, at a gate bias of 25V. The average threshold voltages out of 50 AccuFETs, and InvFETs at Id of 1mA are 2.33V, and 4.27V, respectively. Threshold voltages of both structures show tight distributions across the 6-inch wafer (see Fig. 9).

Field effect channel mobilities were calculated from transconductances measured on lateral MOSFETs with channel length of 200 µm. Fig. 10 shows a good correlation between the accumulation channel mobility and the inversion channel mobility, which may be attributed to common process variations such as the gate oxide thickness and the subsequent annealing. A clear correlation between the threshold voltage and the channel mobility was observed for both AccuFETs and InvFETs as shown in Fig. 11. This correlation is informative to establish the gate oxidation and post oxidation anneal (POA) process. Threshold voltages and channel mobilities at high temperatures were also compared (not shown in this report). It was also proven that no significant deterioration was produced in blocking characteristics by both channel designs.

In summary, the 1.2kV AccuFET structure provides lower on-resistance, and higher transconductance due to higher channel mobility compared with the 1.2kV InvFET. The threshold voltage of the AccuFET structure is about 2V lower than that of the InvFET structure, but still in the acceptable range.

Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) using a Single Ohmic/Schottky Process Scheme [6, 7]

Bipolar operation of the inherent body-diode in a Silicon Carbide (SiC) MOSFET structure is undesirable for reliable device operations and reduced conduction loss. A Schottky contact based unipolar-type diode can be externally connected in parallel to a MOSFET as a separate chip in order to accommodate current in the opposite direction. In this case, the body-diode formed by the p-well and n-drift junction in the MOSFET structure will not turn-on. When a unipolar mode diode is integrated in a MOSFET structure on a single chip, it is beneficial because both MOSFET and diode not only share the forward conducting layer but they also share the edge termination region such that a significant reduction in SiC wafer area can be expected. In addition, this approach will reduce the number of packages in half bringing down the cost of implementing this technology in power converters. It will also improve efficiency and increase switching frequency by eliminating the parasitic inductance between separately packaged devices. Various approaches for a MOSFET and diode pair are summarized in Fig. 12. Panasonic proposed a MOSFET structure integrated with unipolar internal MOS-channel diode. However, since its diode structure is utilizing the MOSFET channel, and a diode requires a certain knee voltage, it is difficult to attain balanced current handling capabilities from both MOSFET and diode at the same forward voltage drops. In addition, n-epitaxial channel needs to be engineered to ensure diode current at reasonable voltage drop, which may bring issues in process latitude, and other reliability concerns in the MOSFET operation. Hestia Power Incorporation and Mitsubishi also demonstrated a MOSFET with embedded diode. In their approaches, Schottky region was formed by a separate metal process.

In this research, a simple method to accomplish a unipolar antiparallel Junction Barrier Schottky (JBS) diode functionality within the SiC MOSFET structure was proposed and experimentally verified for the first time. A simple fabrication scheme has been developed for the proposed JBSFET in order to avoid adding any processing steps to the conventional MOSFET fabrication flow.

Fig. 13(a) shows the layout of the proposed SiC JBSFET. The pure JBS diode area is surrounded by MOSFET cells. It is convenient to place the MOSFET outside because the gate pad does not interrupt the big source pad, which makes the wire bonding easier, and the wire to the gate pad shorter. Area for each MOSFET and JBS diode can be determined through 2-D device simulations to target a specific current. A cross-section of the proposed SiC JBSFET is shown in Fig. 13(b). It is important to note that a single metal, single thermal treatment process was used to simultaneously form ohmic contacts on n+, p+ implanted regions, and Schottky contact on n- 4H-SiC epi-layer. Nickel (Ni) is the most commonly used metal for the ohmic contact formation on n+ region on SiC with a RTA process at higher than 950°C. Ni is also able to form an ohmic contact on p+ implanted region at the same time. However, there are no detailed reports on the formation of n- Schottky contacts simultaneously with n+ and p+ ohmic contacts. For the purpose of this work, Ni is required to remain a Schottky contact on n- epi-layer after the RTA process. Therefore, careful investigation to optimize the RTA condition was required. It was found that Ni can simultaneously form ohmic contacts on n+ and p+ implanted regions while it remains a Schottky contact on the n-epitaxial drift layer when it is annealed at moderate temperature (900°C for 2 min). Fig. 14(a) shows typical output characteristics of the fabricated JBSFET and MOSFET. As expected, the MOSFET has a lower on-resistance than the JBSFET in the forward conduction mode (first quadrant) due to the area consumed by the JBS diode. At the same active area (4.5 mm2), specific on-resistances at drain current of 1A are 7.25 mohm∙cm2 and 12.5 mohm∙cm2 for the MOSFET and the JBSFET, respectively. However, in the third quadrant, the JBSFET provides a very low forward drop due to the conduction of the JBS diode as shown in Fig. 14(b). In contrast to the MOSFET, the JBSFET shows exactly same current-voltage characteristics regardless of the gate biases. It should be noted that it is flexible to achieve a desired current in each first and third quadrant from the JBSFET by allocating appropriate area in its layout design.

Edge termination techniques for high voltage devices on SiC [8, 9]

Conventional edge termination techniques for SiC devices include floating field rings (FFRs), junction termination extension (JTE), and modified JTE structures. Among these edge termination structures, FFRs usually require a narrow definition of the space between rings near the main p+/n junction, and tight control of defects in order to achieve the designed breakdown voltage. It is widely known that a conventional single zone JTE (SZ-JTE) is sensitive to the impurity dose resulting in a sharp peak in breakdown voltage over the JTE implant dose. The optimum JTE dose for the SZ-JTE is about 1×1013 cm-2 based on the Gauss law. To overcome this shortcoming, multiple floating zone JTE (MFZ-JTE) and space modulated JTE (SM-JTE) were proposed, which experimentally verified that high breakdown voltage can be achieved at higher dose in JTE region. Ring assisted JTE (RA-JTE) was proposed to provide high breakdown voltage with a lower JTE dose than the one optimized for the SZ-JTE.

In this research, a Hybrid-JTE that combines MFZ-JTE and RA-JTE is proposed to achieve a near ideal breakdown voltage over a wide range of JTE dose for the first time. A conventional FFR structure that consumes the same area was designed and fabricated at the same time for a comparison purpose.

Fig. 15(a) shows the proposed Hybrid-JTE structure that simply combines a RA-JTE and a MFZ-JTE structure. 40µm thick-, 2×1015cm-3 doped drift layer was chosen to attain 5500V from a parallel plane p+n diode. 35-FFRs was also designed and optimized based on extensive 2-D simulations (Fig. 15(b)). Total width for both Hybrid-JTE and FFRs is 180 µm. Each RA- and MFZ-JTE is designed exclusively and then combined to create the proposed Hybrid-JTE structure.

Fig. 16 shows measured reverse blocking characteristics of the fabricated PiN diodes with the proposed Hybrid-JTE structures and FFRs. The maximum breakdown voltage achieved by using the Hybrid-JTE was 5450V at anode current of 100 µA, which is 99% of the ideal value for a 1-D structure calculated using Konstantinov’s form for the critical electric field for our structure. From most of dies, the leakage current is maintained very low up to 4000V. In contrast, the maximum breakdown voltage from the PiN diode with FFRs was 4160V. Furthermore, a significant increase in leakage current is observed at relatively low voltage at ~2000V. Overall, it was experimentally demonstrated that the Hybrid-JTE provides a nearly ideal breakdown voltage with tight distribution across the wafer. In addition, wider range of JTE implant doses were allowed for achieving high breakdown voltages using the Hybrid-JTE.

Publications

Woongje Sung, and B. J. Baliga, “Design and Economic Considerations to Achieve the Price Parity of SiC MOSFETs with Silicon IGBTs,” Materials Science Forum, Vols. 858, pp. 889-893,2016;
Anant Agarwal, Woongje Sung, Laura Marlino, Pawel Gradzki, John Muth, Robert Ivester, and Nick Justice, “Wide Band Gap Semiconductor Technology for Energy Efficiency,” Materials Science Forum, Vols. 858, pp. 797-802,2016;
Woongje Sung, B. J. Baliga, and Alex Q. Huang, "Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices," IEEE Transaction on Electron Devices, vol.63, no.4, pp.1630-1636, Apr. 2016;
Woongje Sung and B. J. Baliga, “Design and Fabrication of 1400V 4H-SiC Accumulation Mode MOSFETs (ACCUFETs),” proceeding of 11th European Conference on Silicon Carbide and Related Materials, Sep. 25-29, Halkidiki, Greece, 2016
Woongje Sung, Kijeong Han, and B. J. Baliga, “A comparative study of channel designs for SiC MOSFETs: accumulation mode channel vs. inversion mode channel,” Proceedings of International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2017
Woongje Sung and B. J. Baliga, “Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) using a Single Ohmic/Schottky Process Scheme,’’ IEEE Electron Device Lett., vol. 99, Dec. 2016. DOI: 10.1109/LED.2016.2618720
Woongje Sung and B. J. Baliga, “On Developing One-Chip Integration of 1.2kV SiC MOSFET and JBS Diode (JBSFET),” IEEE Transactions on Industrial Electronics, Approved for publication, DOI: 10.1109/TIE.2017.2696515
Woongje Sung and B. J. Baliga, “A Near Ideal Edge Termination Technique for 4500V 4H-SiC Devices: the Hybrid Junction Termination Extension (Hybrid-JTE),’’ IEEE Electron Device Lett., vol. 37, no.12, Dec. 2016. DOI: 10.1109/LED.2016.2623423
Woongje Sung and B. J. Baliga, “A Comparative Study of 4500-V Edge Termination Techniques for SiC Devices,” IEEE Transactions on Electron Devices, vol. 64, Issue 4, Apr. 2017, pp. 1647-1652. DOI: 10.1109/TED.2017.2664051

People

Woongje Sung

Associate Professor, College of Nanoscale Science and Engineering, Principal Investigator

Woongje Sung received his BS and MS degrees in electrical engineering from Korea University in 2000, and 2002 respectively. He received his ph. D. in electrical and computer engineering from North Carolina State University in 2011. He has experience in a number of industrial settings including a startup company, a semiconductor foundry (Dongbu Hitek), and a mature multi-national company (Samsung Advanced Institute of Technology). He is a founding member of DOE funded PowerAmerica Institute, where he has been contributing to establish the baseline process of SiC MOSFETs and diodes. In 2016, He has joined State University of New York Polytechnic Institute (SUNY Poly), CNSE (College of Nanoscale Science and Engineering), as an Associate Professor. He is an author of >30 peer-reviewed publications and 12 U.S. Patents.

Nick (Nung Jun) Yun

Graduate Student (Fall 2017 - Present)

Nick Yun received his BS degree in nanoscale engineering from the State University of New York at Albany (SUNY-Albany) – College of Nanoscale Science and Engineering (CNSE), in 2017. He is currently pursing the PhD degree in nanoscale engineering from SUNY Polytechnic Institute, under the guidance of Dr. Woongje Sung. He has a background research of synthesis and optical characterization of 3C-SiC nanowires and 2D nano-materials. During his time here, he has designed and fabricated 600V to 13kV 4H-SiC MOSFETs, diodes, JBS diode integrated MOSFETs (JBSFETs), and GaN PiN diodes. His major focus is development and manufacturing of ultra-high-voltage SiC MOSFETs, diodes, and JBSFETs (voltage rating: 12-15kV).

Justin Lynch

Undergraduate Student (Fall 2018 - Present)

Justin Lynch is currently a second year graduate student at SUNY Polytechnic Institute, pursuing a PhD in Nanoscale Engineering. He is from Hoosick Falls, New York and received his bachelors degree in Nanoscale Engineering from the Colleges of
Nanoscale Science and Engineering at the University at Albany in May of 2018. Justin joined the team of Dr. Woongje Sung’s research group in 2017, and has spent his time since then studying and fabricating various SiC Power Devices. He is currently involved in:

Development of SiC JFETs
Development and investigations of various ion implantation technics on SiC power device performance

Sundar Babu Isukapati

Graduate Student (Spring 2019 - Present)

Sundar Isukapati received his MS degree in electrical engineering in Youngstown State University. He is a second year graduate student, pursing his PhD in nanoscale engineering from SUNY Polytechnic Institute. He has a background research of fabrication, electrical and optical characterization of -Ga2O3 thin films. As of now, his interests are to develop scalable, manufacturable, and robust technology for SiC power integrated circuits.
He is currently involved in…

SMART SiC Power ICs for Arpa-E

From this project, he has learnt to understand the CMOS technology, fabrication process of each device, and to design and simulate the devices based on their voltage ratings.

Dongyoung Kim

Graduate Student (Spring 2019 - Present)

Dongyoung Kim received his BS and MS degrees in semiconductor engineering from Gyeongsang National University (South Korea) in 2016 and 2018, respectively. He is a second year graduate student, pursing his PhD in nanoscale engineering from SUNY Polytechnic Institute. He has a background research of design and fabrication of 4H-SiC MOSFETs and trench diodes. As of now, his interests are designing and fabricating energy efficient devices utilizing wide-bandgap materials.
He is currently involved in development of 1.2 kV and 12kV 4H-SiC MOSFETs, JBS diodes, and JBS diode integrated MOSFETs (JBSFETs). From these projects, he designs different voltage rating devices, and device fabrication process to make them.

Stephen A. Mancini

Graduate Student (Spring 2020 - Present)

Stephen A. Mancini received his BS degree in nanoscale engineering at SUNY Polytechnic Institute College of Nanoscale Science and Engineering (CNSE). Steve is a first year graduate student, pursuing his PhD in nanoscale engineering from SUNY Polytechnic Institute. Background industry and research includes TCAD modeling of stress and its impacts on wafer warpage, and 3D NAND device modeling. He is now looking to further his understanding and interests in the design and fabrication of SiC power devices.
Current Projects involved in…

Improving SiC Wafers and Processing for Lower Costs and Higher Reliability.

Adam J Morgan, PhD

Postdoctoral Research Scientist (Fall 2019 - Present)

Dr. Adam J Morgan received his PhD in Electrical Engineering at North Carolina State University where he was a graduate research assistant within the Future Renewable Electric Energy Delivery and Management (FREEDM) Systems Center, PowerAmerica, and the Packaging Research in Electronic Energy Systems (PREES) Laboratory. He has experience in Level-1 power discrete and power module packaging for hybrid Si&SiC motor contactors and super cascode topologies, as well as Level-2 and Level-3 power packaging for a 55 kW traction drive SiC inverter and a 1 kW self-oscillating resonant LLC converter switching 1 kV at 1 MHz.
He is currently involved in…

WBG power semiconductor device research via high temperature (150 oC to 300 oC) and high voltage (600 V to 25 kV) power packaging and power electronics testing.

Publications

Papers

Nick Yun, Woongje Sung et al, “On the development of 1700V SiC JBS diodes in a 6-inch foundry,” accepted for a presentation, European Conferences on Silicon Carbide and Related Materials (ECSCRM), 2018

Kijeong Han, B. J. Baliga, and Woongje Sung “Accumulation channel vs. Inversion channel 1.2kV rated 4H-SiC Buffered-Gate (BG) MOSFETs: Analysis and Experimental Results,” Proceedings of ISPSD, 2018.

Woongje Sung, Kijeong Han, and B. J. Baliga, “Optimization of the JFET region of 1.2kV SiC MOSFETs for improved high frequency figure of merit (HF-FOM),” Proceeding of Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2017.

Woongje Sung, Kijeong Han, and B. J. Baliga, “Design and Manufacturing of 1200V SiC JBS Diodes with Low On-state Voltage Drop and Reverse Blocking Leakage Current,” Proceeding of International Conferences on Silicon Carbide and Related Materials (ICSCRM), 2017

B. J. Baliga, Woongje Sung, Kijeong Han, Jeffrey Harmon, Austin Tucker, Saimum Syed, “PRESiCE: Process Engineered for manufacturing SiC Electronic-devices,” Proceeding of International Conferences on Silicon Carbide and Related Materials (ICSCRM), 2017

Kijeong Han, B. J. Baliga, and Woongje Sung, “1.2kV Split-Gate MOSFET: Analysis and Experimental Results,” Proceeding of International Conferences on Silicon Carbide and Related Materials (ICSCRM), 2017

Kijeong Han, B. J. Baliga, and Woongje Sung, “Split-Gate 1.2kV 4H-SiC MOSFET: Analysis and Experimental Validation,” IEEE Electron Device Lett., vol. 38, no. 10, pp. 1437-1440, Oct. 2017. DOI: 10.1109/LED.2017.2738616

Yifan Jiang, Woongje Sung, Jayant Baliga, Sizhen Wang, Bongmook Lee, and A. Q. Huang, “Electrical Characteristics of 10kV 4H-SiC MPS Rectifiers with High Schottky Barrier Height,” Journal of Electronic Materials, 2017, DOI: https://doi.org/10.1007/s11664-017-5812-2

Woongje Sung, Kijeong Han, and B. J. Baliga, “A comparative study of channel designs for SiC MOSFETs: accumulation mode channel vs. inversion mode channel,” Proceedings of International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2017.

Woongje Sung and B. J. Baliga, "On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)," IEEE Transaction on Industrial Electronics, vol.64, no.10, pp. 8206-8212, Oct. 2017; DOI: 10.1109/TIE.2017.2696515

Woongje Sung and B. J. Baliga, “Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) using a Single Ohmic/Schottky Process Scheme,’’ IEEE Electron Device Lett., vol. 37, no. 12, pp. 1605-1608, Dec. 2016. DOI: 10.1109/LED.2016.2618720

Woongje Sung and B. J. Baliga, “A Near Ideal Edge Termination Technique for 4500V 4H-SiC Devices: the Hybrid Junction Termination Extension (Hybrid-JTE),’’ IEEE Electron Device Lett., vol. 37, no.12, pp. 1609-1612, Dec. 2016. DOI: 10.1109/LED.2016.2623423

Woongje Sung and B. J. Baliga, “Design and Fabrication of 1400V 4H-SiC Accumulation Mode MOSFETs (ACCUFETs),” proceeding of 11th European Conference on Silicon Carbide and Related Materials, Sep. 25-29, Halkidiki, Greece, 2016

Woongje Sung, B. J. Baliga, and Alex Q. Huang, "Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices," IEEE Transaction on Electron Devices, vol.63, no.4, pp.1630-1636, Apr. 2016.

Siyang Liu, Yifan Jiang, Woongje Sung, Xiao Qing Song, B. J. Baliga, Wei Feng Sung, and Alex Q. Huang, “Understanding High Temperature Static and Dynamic Characteristics of 1.2kV SiC Power MOSFETs,” Material Science Forum, Vol. 897, pp. 501-504, 2017

Yifan Jiang, Woongje Sung, Xiaoqing Song, Haotao Ke, Siyang Liu, B. J. Baliga, A. Q. Huang, and Edward Van Brunt, “10kV SiC MPS diodes for high temperature applications,” Proceedings of International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 43-46, 12-16, June, 2016

Anant Agarwal, Woongje Sung, Laura Marlino, Pawel Gradzki, John Muth, Robert Ivester, and Nick Justice, “Wide Band Gap Semiconductor Technology for Energy Efficiency,” Materials Science Forum, Vols. 858, pp. 797-802,2016;

Woongje Sung, and B. J. Baliga, “Design and Economic Considerations to Achieve the Price Parity of SiC MOSFETs with Silicon IGBTs,” Materials Science Forum, Vols. 858, pp. 889-893,2016;

Woongje Sung, Alex Q. Huang, and B. J. Baliga, “Bevel Junction Termination Extension (Bevel-JTE) – A New Edge Termination Technique for 4H-SiC High Voltage Devices,” Electron Device Letters, IEEE , vol.36, no.6, pp.594-596, June 2015;

Lin Liang, Alex Q. Huang, Woongje Sung, Meng-Chia Lee, Xiaoqing Song, Chang Peng, Lin Cheng, John Palmour, Charles Scozzie, “Turn-on Capability of 22kV SiC Emitter Turn-Off (ETO) Thyristor,” Proceeding of Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2015.

Woongje Sung, Alex Q. Huang, B. J. Baliga, Inhwan Ji, Haotao Ke, Douglas C. Hopkins, “The First Demonstration of Symmetric Blocking SiC P-type Gate Turn-Off (GTO) Thyristor,” Proceedings of ISPSD 2015, pp. 257-260, 10-14, May, 2015

Lin Cheng, John W. Palmour, Anant K. Agarwal, Scott T. Allen, Edward V. Brunt, Gangyao Wang, Vipindas Pala, Woongje Sung, Alex Q. Huang, Michael O’Loughlin, Albert Burk, Dave Grider, and Charles Scozzie, “Strategic Overview of High-Voltage SiC Power Device Development Aiming at Global Energy Savings,” Materials Science Forum, Vols. 778-780, pp. 1089-1095, 2014

Woongje Sung, E. V. Brunt, B. J. Baliga, and Alex Q. Huang, "A Comparative Study of Gate Structures for 9.4-kV 4H-SiC Normally On Vertical JFETs," IEEE Transaction on Electron Devices, vol.59, no.9, pp.2417-2423, Sept. 2012;

Woongje Sung, E. V. Brunt, B. J. Baliga, and Alex Q. Huang, "A New Edge Termination Technique for High-Voltage Devices in 4H-SiC – Multiple-Floating-Zone Junction Termination Extension," Electron Device Letters, IEEE , vol.32, no.7, pp.880-882, July 2011;

Woongje Sung, B. J. Baliga, and A. Q. Huang, “A Novel 4H-SiC Fault Isolation Device with Improved Trade-off between On-state Voltage Drop and Short Circuit SOA,” Materials Science Forum, Vols. 717-720, pp. 1045-1048,2012;

Woongje Sung, A. Q. Huang, and B. J. Baliga, “A novel 4H-SiC IGBT structure with improved trade-off between short circuit capability and on-state voltage drop,” Proceedings of ISPSD 2010, pp. 217-220, 6-10, June, 2010;

Woongje Sung, Jun Wang, A. Q. Huang, and B. J. Baliga, “Design and investigation of frequency capability of 15kV 4H-SiC IGBT,” Proceedings of ISPSD 2009, pp. 271-274, 14-18, June, 2009;

Jun Wang, A. Q. Huang, Woongje Sung, Yu, Liu, B. J. Baliga, “Development of 15kV SiC IGBTs and Their Impact to Utility Application,” IEEE Industrial Electronics Magazine, March 2009;

Woo Beom Choi, Woongje Sung, Chun Il Park, Sangsig Kim, Man Young Sung, “New lateral insulated-gate bipolar transistor on silicon-on-insulator,” Journal of the Korean Physical Society, Vol. 40, Issue 4, pp. 645-648, 2002;

Man Young Sung, Woongje Sung, Yong Il Lee, Chun Il Park, Woo Beom Choi, Sangsig Kim, “Effect of excimer laser annealing on optical properties of GaN films deposited by RF magnetron sputtering,” Materials Research Society Symposium - Proceedings, Vol. 693, pp. 61-66, 2002;

Woo Beom Choi, Woongje Sung, Yong Il Lee, Man Young Sung, “A new silicon-on-insulator lateral insulated-gate bipolar transistor with dual channel structure,” Japanese journal of applied physics, Vol. 40, Issue 12R, p. 6683, 2001;

Woo Beom Choi, Woongje Sung, Yong Il Lee, Man Young Sung, “Dual channel SOI LIGBT with improved latch-up and forward voltage drop characteristics,” Device Research Conference 2001, pp. 53-54;

Woongje Sung, Yong Il Lee, Woo Beom Choi, Man Young Sung, “A New SOI LIGBT Structure with Improved Latch-up Performance,” Transaction on Electrical and Electronic Materials Vol.2, Issue 4, 2001, pp. 30-32;

Patents

7018899 Methods of Fabricating Lateral Double-Diffused Metal Oxide Semiconductor Devices, Woongje Sung, Mar. 28, 2006

7247507, Methods for Forming LOCOS Layer in Semiconductor Device, Woongje Sung, Jul. 24, 2007

7329584, Method for manufacturing bipolar transistor, Woongje Sung, Feb. 12, 2008

7482238, Methods for Manufacturing Semiconductor Device, Woongje Sung, Jan. 27, 2009

7446013, Method of measuring pattern shift in semiconductor device, Woongje Sung, Nov. 4, 2008

7439147, Resistor of Semiconductor device and method for fabricating the same, Woongje Sung, Oct. 21, 2008

7442617, Method for manufacturing bipolar transistor, Woongje Sung, Oct. 28, 2008

7595535, Resistor of Semiconductor device and method for fabricating the same, Woongje Sung, Sep. 29, 2009

7674681, Semiconductor device and method for manufacturing the same, Woongje Sung, Mar. 9, 2010

7727851, Method of measuring shifted epitaxy layer by buried layer, Woongje Sung, Jun. 1, 2010

9129835, Semiconductor device and method for manufacturing then same, Woongje Sung, Chang-yong Um, Jai-kwang Shin, Sep. 8, 2015

9053964, Semiconductor devices including a first and second HFET and methods of manufacturing the same, Woo-cheol Jeon, Woongje Sung, Jai-kwang Shin, Jae-joon Oh, Jun. 9, 2015

News

SUNY Poly scientists win major federal grant for research
https://www.timesunion.com/business/article/SUNY-Poly-prof-wins-major-federal-grant-for-14114302.php

Sung awarded $2.1 million by Department of Energy
https://altamontenterprise.com/09182019/sung-awarded-21-million-department-energy

SUNY Poly Professor Awarded U.S. Department of Energy Grant as Part of Overall $750,000 Project to Develop More Efficient, Cost-Effective Power Electronics Chips
https://www.sunypoly.edu/news/suny-poly-professor-awarded-us-department-energy-grant-part-overall-750000-project-develop.html

SUNY Poly professor receives large grant (Video)
https://cbs6albany.com/news/local/suny-poly-professor-receives-large-grant

New Manufacturing Process for SiC Power Devices Opens Market to More Competition
https://news.ncsu.edu/2017/09/presice-2017/

New York Power Electronics Manufacturing Consortium Headquartered at SUNY Poly Announces Successful First Production of Silicon Carbide-Based Patterned Wafers
https://sunypoly.edu/news/new-york-power-electronics-manufacturing-consortium-headquartered-suny-poly-announces.html

Funding

Advanced Manufacturing Office (AMO/ DOE)
Vehicle Technology Office (VTO/ DOE)
PowerAmerica
Advanced Research Projects Agency- energy (Arpa-e/ DOE)
Army Research Lab, Office of Naval Research (ONR)
Center for Advanced Technology in Nanomaterials and Nanoelectronics (CATN2)
NISSIN Ion Equipment

Department of Energy United States of America

CATN2 Center for Advanced Technology in Nanomaterials and Nanoelectronics

Office of Naval Research Science & Technology

US Department of Energy | Energy Efficiency & Renewable Energy Vehicle Technology Office